欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2320-I/SP的Datasheet PDF文件第162页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第163页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第164页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第165页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第167页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第168页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第169页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第170页  
PIC18F2220/2320/4220/4320  
2
17.4.1  
REGISTERS  
17.4 I C Mode  
The MSSP module has six registers for I2C operation.  
These are:  
The MSSP module in I2C mode fully implements all  
master and slave functions (including general call sup-  
port) and provides interrupts on Start and Stop bits in  
hardware to determine a free bus (multi-master func-  
tion). The MSSP module implements the standard  
mode specifications, as well as 7-bit and 10-bit  
addressing.  
• MSSP Control Register 1 (SSPCON1)  
• MSSP Control Register 2 (SSPCON2)  
• MSSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer (SSPBUF)  
• MSSP Shift Register (SSPSR) – Not directly  
accessible  
Two pins are used for data transfer:  
• Serial Clock (SCL) – RC3/SCK/SCL  
• Serial Data (SDA) – RC4/SDI/SDA  
• MSSP Address Register (SSPADD)  
SSPCON1, SSPCON2 and SSPSTAT are the control  
and status registers in I2C mode operation. The  
SSPCON1 and SSPCON2 registers are readable and  
writable. The lower six bits of the SSPSTAT are  
read-only. The upper two bits of the SSPSTAT are  
read/write.  
The user must configure these pins as inputs using the  
TRISC<4:3> bits.  
FIGURE 17-7:  
MSSP BLOCK DIAGRAM  
(I2C MODE)  
SSPSR is the shift register used for shifting data in or  
out. SSPBUF is the buffer register to which data bytes  
are written to or read from.  
Internal  
Data Bus  
Read  
Write  
SSPADD register holds the slave device address  
when the SSP is configured in I2C Slave mode. When  
the SSP is configured in Master mode, the lower  
seven bits of SSPADD act as the Baud Rate  
Generator reload value.  
SSPBUF reg  
Shift  
Clock  
RC3/SCK/  
SCL  
In receive operations, SSPSR and SSPBUF together  
create a double-buffered receiver. When SSPSR  
receives a complete byte, it is transferred to SSPBUF  
and the SSPIF interrupt is set.  
SSPSR reg  
RC4/SDI/  
SDA  
MSb  
LSb  
Addr Match  
Match Detect  
SSPADD reg  
During transmission, the SSPBUF is not double-  
buffered. A write to SSPBUF will write to both SSPBUF  
and SSPSR.  
Set, Reset  
S, P bits  
(SSPSTAT reg)  
Start and  
Stop bit Detect  
DS39599C-page 164  
2003 Microchip Technology Inc.  
 复制成功!