PIC17C4X
5.2
Peripheral Interrupt Enable Register
(PIE)
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 5-3: PIE REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE
RCIE
bit7
bit0
bit 7:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TMR3IE: Timer3 Interrupt Enable bit
1 = Enable Timer3 interrupt
0 = Disable Timer3 interrupt
TMR2IE: Timer2 Interrupt Enable bit
1 = Enable Timer2 interrupt
0 = Disable Timer2 interrupt
TMR1IE: Timer1 Interrupt Enable bit
1 = Enable Timer1 interrupt
0 = Disable Timer1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture interrupt on RB1/CAP2 pin
0 = Disable Capture interrupt on RB1/CAP2 pin
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture interrupt on RB2/CAP1 pin
0 = Disable Capture interrupt on RB2/CAP1 pin
TXIE: USART Transmit Interrupt Enable bit
1 = Enable Transmit buffer empty interrupt
0 = Disable Transmit buffer empty interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enable Receive buffer full interrupt
0 = Disable Receive buffer full interrupt
1996 Microchip Technology Inc.
DS30412C-page 23
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