PIC17C4X
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Address
Power-on Reset
Unbanked
INDF0
FSR0
00h
01h
02h
0000 0000
xxxx xxxx
0000h
0000 0000
uuuu uuuu
0000h
0000 0000
uuuu uuuu
PC + 1(2)
uuuu uuuu
1111 uuuu
0000 000-
--uu qq--
PCL
PCLATH
ALUSTA
T0STA
03h
04h
05h
06h
0000 0000
1111 xxxx
0000 000-
--11 11--
0000 0000
1111 uuuu
0000 000-
--11 qq--
CPUSTA(3)
uuuu uuuu(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
INTSTA
07h
0000 0000
0000 0000
INDF1
FSR1
08h
09h
0Ah
0Bh
0Ch
0Dh
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WREG
TMR0L
TMR0H
TBLPTRL (4)
TBLPTRH (4)
TBLPTRL (5)
0Eh
0Dh
0Eh
0Fh
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLPTRH (5)
BSR
Bank 0
PORTA
DDRB
10h
11h
12h
13h
14h
15h
16h
17h
0-xx xxxx
1111 1111
xxxx xxxx
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
xxxx xxxx
0-uu uuuu
1111 1111
uuuu uuuu
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
Bank 1
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
10h
11h
12h
13h
14h
15h
16h
1111 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- -111
---- -xxx
0000 0010
1111 1111
uuuu uuuu
1111 1111
uuuu uuuu
---- -111
---- -uuu
0000 0010
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---- -uuu
uuuu uuuu(1)
PIE
17h
0000 0000
0000 0000
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 4-3 for reset value of specific condition.
4: Only applies to the PIC17C42.
5: Does not apply to the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 19
MICROCHIP [ MICROCHIP ]
