欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16C71-04/SO 参数 Datasheet PDF下载

PIC16C71-04/SO图片预览
型号: PIC16C71-04/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器与A / D转换器 [8-Bit CMOS Microcontrollers with A/D Converter]
分类和应用: 转换器微控制器
文件页数/大小: 176 页 / 1596 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16C71-04/SO的Datasheet PDF文件第13页浏览型号PIC16C71-04/SO的Datasheet PDF文件第14页浏览型号PIC16C71-04/SO的Datasheet PDF文件第15页浏览型号PIC16C71-04/SO的Datasheet PDF文件第16页浏览型号PIC16C71-04/SO的Datasheet PDF文件第18页浏览型号PIC16C71-04/SO的Datasheet PDF文件第19页浏览型号PIC16C71-04/SO的Datasheet PDF文件第20页浏览型号PIC16C71-04/SO的Datasheet PDF文件第21页  
PIC16C71X  
4.2.2.1  
STATUS REGISTER  
It is recommended, therefore, that only BCF, BSF,  
SWAPF and MOVWF instructions are used to alter the  
STATUS register because these instructions do not  
affect the Z, C or DC bits from the STATUS register. For  
other instructions, not affecting any status bits, see the  
"Instruction Set Summary."  
Applicable Devices 710 71 711 715  
The STATUS register, shown in Figure 4-7, contains  
the arithmetic status of the ALU, the RESET status and  
the bank select bits for data memory.  
Note 1: For those devices that do not use bits IRP  
and RP1 (STATUS<7:6>), maintain these  
bits clear to ensure upward compatibility  
with future products.  
The STATUS register can be the destination for any  
instruction, as with any other register. If the STATUS  
register is the destination for an instruction that affects  
the Z, DC or C bits, then the write to these three bits is  
disabled.These bits are set or cleared according to the  
device logic. Furthermore, the TO and PD bits are not  
writable. Therefore, the result of an instruction with the  
STATUS register as destination may be different than  
intended.  
Note 2: The C and DC bits operate as a borrow  
and digit borrow bit, respectively, in sub-  
traction. See the SUBLW and SUBWF  
instructions for examples.  
For example, CLRF STATUSwill clear the upper-three  
bits and set the Z bit. This leaves the STATUS register  
as 000u u1uu(where u= unchanged).  
FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h)  
R/W-0  
IRP  
R/W-0  
RP1  
R/W-0  
RP0  
R-1  
TO  
R-1  
PD  
R/W-x  
Z
R/W-x  
DC  
R/W-x  
C
R = Readable bit  
W = Writable bit  
bit7  
bit0  
U = Unimplemented bit,  
read as ‘0’  
- n = Value at POR reset  
bit 7:  
IRP: Register Bank Select bit (used for indirect addressing)  
1 = Bank 2, 3 (100h - 1FFh)  
0 = Bank 0, 1 (00h - FFh)  
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)  
11= Bank 3 (180h - 1FFh)  
10= Bank 2 (100h - 17Fh)  
01= Bank 1 (80h - FFh)  
00= Bank 0 (00h - 7Fh)  
Each bank is 128 bytes  
bit 4:  
bit 3:  
bit 2:  
bit 1:  
bit 0:  
TO: Time-out bit  
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction  
0 = A WDT time-out occurred  
PD: Power-down bit  
1 = After power-up or by the CLRWDTinstruction  
0 = By execution of the SLEEPinstruction  
Z: Zero bit  
1 = The result of an arithmetic or logic operation is zero  
0 = The result of an arithmetic or logic operation is not zero  
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)  
1 = A carry-out from the 4th low order bit of the result occurred  
0 = No carry-out from the 4th low order bit of the result  
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)  
1 = A carry-out from the most significant bit of the result occurred  
0 = No carry-out from the most significant bit of the result occurred  
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of  
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order  
bit of the source register.  
1997 Microchip Technology Inc.  
DS30272A-page 17  
 
 复制成功!