PIC16C71X
4.2.2
SPECIAL FUNCTION REGISTERS
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral
feature.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(1)
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
01h
TMR0
PCL
02h(3)
03h(3)
Program Counter's (PC) Least Significant Byte
IRP(5)
RP1(5)
STATUS
RP0
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
TO
PD
Z
DC
C
04h(3)
05h
FSR
xxxx xxxx uuuu uuuu
---x 0000 ---u 0000
xxxx xxxx uuuu uuuu
PORTA
PORTB
—
—
—
—
06h
PORTB Data Latch when written: PORTB pins when read
Unimplemented
07h
—
—
08h
ADCON0
ADRES
ADCS1
ADCS0
(6)
CHS1
CHS0
GO/DONE
ADIF
ADON
00-0 0000 00-0 0000
xxxx xxxx uuuu uuuu
09h(3)
A/D Result Register
0Ah(2,3)
PCLATH
INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
0Bh(3)
GIE
ADIE
T0IE
Bank 1
80h(3)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(3)
83h(3)
IRP(5)
RP1(5)
STATUS
PD
Z
DC
C
84h(3)
85h
FSR
xxxx xxxx uuuu uuuu
---1 1111 ---1 1111
1111 1111 1111 1111
---- --qq ---- --uu
---- --00 ---- --00
xxxx xxxx uuuu uuuu
TRISA
TRISB
PCON
ADCON1
ADRES
—
—
—
PORTA Data Direction Register
86h
PORTB Data Direction Control Register
87h(4)
88h
—
—
—
—
—
—
—
—
—
—
—
—
POR
BOR
PCFG1
PCFG0
89h(3)
A/D Result Register
8Ah(2,3)
8Bh(3)
PCLATH
INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
GIE
ADIE
T0IE
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: These registers can be addressed from either bank.
4: The PCON register is not physically implemented in the PIC16C71, read as ’0’.
5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.
6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,
read as '0'.
DS30272A-page 14
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
