PIC16C71X
FIGURE 4-5: PIC16C711 REGISTER FILE
MAP
FIGURE 4-6: PIC16C715 REGISTER FILE
MAP
File
File
File
File
Address
Address
Address
Address
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
TMR0
PCL
OPTION
PCL
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PORTA
PORTB
TRISA
TRISB
PCON
ADCON1
ADCON0
ADRES
ADRES
PCLATH
INTCON
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCLATH
INTCON
General
Purpose
Register
PCON
General
Purpose
Register
Mapped
(2)
in Bank 0
CFh
D0h
4Fh
50h
FFh
7Fh
Bank 0
Bank 1
ADRES
Unimplemented data memory locations, read
as '0'.
ADCON0
ADCON1
Note 1: Not a physical register.
A0h
General
Purpose
Register
General
Purpose
Register
2: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
BFh
C0h
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
1997 Microchip Technology Inc.
DS30272A-page 13
MICROCHIP [ MICROCHIP ]
