PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 3
180h
INDF(3)
OPTION_REG RBPU
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
181h
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
PCL(3)
182h
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
STATUS(3)
183h
PD
Z
DC
FSR(3)
—
184h
185h
186h
187h
188h
189h
18Ah
Indirect data memory address pointer
Unimplemented
xxxx xxxx uuuu uuuu
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
Write Buffer for the upper 5 bits of the Program Counter
PCLATH(1,3)
INTCON(3)
—
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
18Ch-
18Fh
—
Unimplemented
—
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
UIR
—
—
—
—
STALL
STALL
UIDLE
UIDLE
TOK_DNE
TOK_DNE
DFN8
ACTIVITY
ACTIVITY
CRC16
CRC16
IN
UERR
UERR
CRC5
CRC5
—
USB_RST --00 0000 --00 0000
USB_RST --00 0000 --00 0000
PID_ERR 0000 0000 0000 0000
PID_ERR 0000 0000 0000 0000
UIE
UEIR
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
UEIE
DFN8
USTAT
UCTRL
UADDR
USWSTAT
UEP0
UEP1
UEP2
—
—
—
—
—
—
ENDP1
PKT_DIS
ADDR4
ENDP0
—
—
---x xx-- ---u uu--
--x0 000- --xq qqq-
SEO
DEV_ATT
ADDR3
RESUME
ADDR2
SWSTAT2
SUSPND
ADDR1
ADDR6
ADDR5
ADDR0 -000 0000 -000 0000
SWSTAT7 SWSTAT6 SWSTAT5 SWSTAT4
SWSTAT3
SWSTAT1 SWSTAT0 0000 0000 0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Bh-
19Fh
Reserved
Reserved, do not use.
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124A-page 20
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
