PIC16C745/765
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF(3)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xx-- -xxx uu-- -uuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
PCL(3)
Program Counter's (PC) Least Significant Byte
STATUS(3)
FSR(3)
IRP(2)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
RC7 RC6
RP1(2)
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
—
—
RC2
RC1
RE1
RC0
—
—
—
PORTD(4) PORTD Data Latch when written: PORTD pins when read
PORTE(4)
PCLATH(1,3)
INTCON(3)
PIR1
—
—
—
—
—
—
—
—
RE2
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
–
RBIE
USBIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(4)
—
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
PIR2
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0
T1OSCEN
T1SYNC
TMR1CS TMR1ON --00 0000 --uu uuuu
0000 0000 0000 0000
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1
T2CON
—
—
TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000 -000 0000
Unimplemented
—
—
—
—
—
Unimplemented
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
DC1B1
SREN
DC1B0
CREN
CCP1M3
—
CCP1M2
FERR
CCP1M1
OERR
CCP1M0 --00 0000 --00 0000
SPEN
RX9
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
DC2B1
CHS2
DC2B1
CHS1
CCP2M3
CHS0
CCP2M2
CCP2M1
—
CCP2M0 --00 0000 --00 0000
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
GO/DONE
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 17
MICROCHIP [ MICROCHIP ]
