PIC16C745/765
FIGURE 4-2: DATA MEMORY MAP FOR PIC16C745/765
Bank 0
File
Bank 1
File
Bank 2
File
Bank 3
File
Address
Address
Address
Address
Indirect addr.(*)
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
Indirect addr.(*)
OPTION_REG
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
Indirect addr.(*)
TMR0
100h
101h
102h
103h
104h
105h
106h
107h
108h
Indirect addr.(*)
OPTION_REG
PCL
180h
181h
182h
183h
184h
185h
186h
187h
188h
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
TRISA
TRISB
PORTB
TRISB
TRISC
(2)
(2)
PORTD
TRISD
(2)
(2)
09h
89h
109h
189h
PORTE
TRISE
PCLATH
INTCON
PIR1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
PCLATH
INTCON
PIE1
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
PCLATH
INTCON
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
PCLATH
INTCON
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
UIR
UIE
T2CON
PR2
UEIR
UEIE
USTAT
UCTRL
UADDR
CCPR1L
CCPR1H
CCP1CON
(1)
USWSTAT
RCSTA
TXREG
RCREG
CCPR2L
18h
19h
1Ah
1Bh
TXSTA
98h
99h
9Ah
9Bh
118h
119h
11Ah
11Bh
UEP0
UEP1
UEP2
198h
199h
19Ah
SPBRG
(1)
19Bh
(1)
CCPR2H
CCP2CON
ADRESH
ADCON0
1Ch
1Dh
1Eh
1Fh
20h
9Ch
9Dh
9Eh
9Fh
A0h
11Ch
11Dh
11Eh
11Fh
120h
19Ch
(1)
19Dh
(1)
19Eh
(1)
ADCON1
19Fh
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
USB Dual Port
Memory
64 Bytes
1A0h
1DFh
1E0h
1EFh
1F0h
1FFh
EFh
F0h
FFh
16Fh
170h
17Fh
accesses
70h-7Fh
accesses
70h-7Fh
accesses
70h-7Fh
7Fh
Unimplemented data memory locations, read as ‘0’.
*Not a physical register.
Note 1: Reserved registers may contain USB state information.
2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745; always maintain these bits clear.
DS41124A-page 16
Advanced Information
1999 Microchip Technology Inc.