PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF(3)
OPTION
PCL(3)
STATUS(3)
FSR(3)
TRISA
TRISB
TRISC
TRISD(4)
TRISE(4)
PCLATH(1,3)
INTCON(3)
PIE1
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
11-- -111 11-- -111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
PORTB Data Direction Register
TRISC7 TRISC8
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
PD
Z
DC
—
—
TRISC2
TRISC1
TRISC0
—
—
—
—
PORTD Data Direction Register
IBF
—
OBF
—
IBOV
—
PSPMODE
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIE
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
USBIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
PSPIE(4)
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PIE2
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PR2
1111 1111 1111 1111
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124A-page 18
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
