PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 2
100h
INDF(3)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
101h
PCL(3)
102h
Program Counter's (PC) Least Significant Byte
STATUS(3)
103h
IRP
RP1
RP0
TO
PD
Z
DC
C
FSR(3)
—
104h
Indirect data memory address pointer
Unimplemented
105h
106h
107h
108h
109h
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PCLATH(1,3)
INTCON(3)
10Ah
10Bh
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF
---0 0000 ---0 0000
0000 000x 0000 000u
GIE
PEIE
T0IE
RBIF
10Ch-
11Fh
—
Unimplemented
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 19
MICROCHIP [ MICROCHIP ]
