PIC16C745/765
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
4.1
Program Memory Organization
The PIC16C745/765 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. All devices covered by this datasheet have 8K x
14 bits of program memory. The address range is
0000h - 1FFFh for all devices.
RP<1:0> (STATUS<6:5>)
= 00→ Bank0
= 01→ Bank1
The reset vector is at 0000h and the interrupt vector is
at 0004h.
= 10→ Bank2
= 11→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
FIGURE 4-1: PIC16C745/765 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
CALL, RETURN
RETFIE, RETLW
13
4.2.1
GENERAL PURPOSE REGISTER FILE
Stack Level 1
Stack Level 2
The register file can be accessed either directly or indi-
rectly through the File Select Register (FSR)
(Section 4.5).
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
Page 1
Page 2
On-chip
Program
Memory
0FFFh
1000h
17FFh
1800h
Page 3
1FFFh
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 15
MICROCHIP [ MICROCHIP ]
