PIC16F716
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY BANK 0
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
00h
01h
02h
INDF(1)
TMR0
PCL(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
xxxx xxxx
0000 0000
18
27
17
Program Counter’s (PC) Least Significant Byte
03h
STATUS(1)
FSR(1)
PORTA(5,6)
PORTB(5,6)
—
PCLATH(1,2)
INTCON(1)
PIR1
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x 0000
xxxx xxxx
—
11
18
19
21
04h
Indirect Data Memory Address Pointer
(7)
05h
—
—
—
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
06h
RB7
RB6
RB5
07h-09h
0Ah
Unimplemented
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
-0-- -000
—
17
13
15
0Bh
GIE
PEIE
ADIF
INTE
—
RBIE
—
T0IF
INTF
RBIF
0Ch
0Dh
0Eh
—
CCP1IF
TMR2IF
TMR1IF
—
Unimplemented
TMR1L
TMR1H
T1CON
TMR2
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
29
29
32
35
36
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Timer2 Module’s Register
TMR1CS TMR1ON --00 0000
11h
0000 0000
12h
T2CON
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
13h-14h
15h
Unimplemented
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
00-0 0000
—
48
48
48
60
57
16h
17h
P1M1
P1M0
PDC6
DC1B1
PDC5
DC1B0
PDC4
CCP1M3
PDC3
CCP1M2
PDC2
CCP1M1
PDC1
CCP1M0
PDC0
18h
PRSEN
(8)
19h
ECCPASE ECCPAS2
Unimplemented
—
ECCPAS0 PSSAC1
PSSAC0
PSSBD1
PSSBD0
1Ah-1Dh
1Eh
ADRES
A/D Result Register
xxxx xxxx
37
41
(7)
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, – = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Note 1:
2:
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3:
4:
5:
6:
7:
8:
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the PORT output latch.
Reserved bits, do not use.
ECCPAS1 bit is not used on PIC16F716.
© 2007 Microchip Technology Inc.
DS41206B-page 9
MICROCHIP [ MICROCHIP ]
