PIC16F716
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 of the STATUS register are the bank select
bits.
There are two memory blocks in the PIC16F716
device. Each block (program memory and data
memory) has its own bus so that concurrent access
can occur.
2.1
Program Memory Organization
RP<1:0>(1)
Bank
(Status<6:5>)
The PIC16F716 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. The
PIC16F716 has 2K x 14 words of program memory.
Accessing a location above the physically implemented
address will cause a wrap-around.
00
01
10
11
0
1
2(2)
3(2)
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
Note 1: Maintain Status bit 6 clear to ensure
upward compatibility with future products.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK OF
PIC16F716
2: Not implemented
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
PC<12:0>
13
Registers
are
General
Purpose
Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. The upper 16
bytes of GPR space and some “high use” Special
Function Registers in Bank 0 are mirrored in Bank 1 for
code reduction and quicker access.
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
07FFh
0800h
1FFFh
© 2007 Microchip Technology Inc.
DS41206B-page 7
MICROCHIP [ MICROCHIP ]
