PIC16F716
TABLE 2-2:
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
80h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
18
81h
82h
OPTION_REG
PCL(1)
RBPU
Program Counter’s (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
12
17
83h
STATUS(1)
FSR(1)
TRISA
TRISB
—
PCLATH(1,2)
INTCON(1)
PIE1
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
11
18
19
21
84h
Indirect Data Memory Address Pointer
(7)
85h
—
—
—
TRISA4
TRISA3
TRISB3
TRISA2
TRISB2
TRISA1
TRISB1
TRISA0
TRISB0
86h
TRISB7
TRISB6
TRISB5 TRISB4
87h-89h
8Ah
8Bh
8Ch
8Dh
Unimplemented
—
GIE
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
-0-- -000
—
17
13
14
PEIE
ADIE
INTE
—
RBIE
—
T0IF
INTF
RBIF
CCP1IE
TMR2IE
TMR1IE
—
Unimplemented
8Eh
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq
—
16
35, 52
42
8Fh-91h
92h
Unimplemented
Timer2 Period Register
Unimplemented
PR2
1111 1111
—
93h-9Eh
9Fh
—
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
Legend:
x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the PORT output latch.
7: Reserved bits, do not use.
DS41206B-page 10
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
