PIC16F/LF1946/47
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CCPxCON
CCPRxL
CCPRxH
INTCON
PIE1
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
229
208*
208*
89
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
GIE
TMR1GIE
OSFIE
—
PEIE
ADIE
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
TMR0IF
CCP1IE
LCDIE
—
INTF
IOCIF
TMR1IE
CCP2IE
—
TMR2IE
—
90
PIE2
C2IE
C1IE
EEIE
BCLIE
91
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR6IE
SSPIF
TMR4IE
TMR2IF
—
92
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
94
PIR2
C2IF
C1IF
EEIF
BCLIF
95
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
T1OSCEN
TMR4IF
—
96
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
TRISC
TRISD
TRISE
TMR1CS<1:0>
T1CKPS<1:0>
T1SYNC
TMR1ON
199
200
195*
195*
124
127
130
133
136
TMR1GE
T1GPOL
T1GTM
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 209
MICROCHIP [ MICROCHIP ]
