PIC16C63A/65B/73B/74B
FIGURE 16-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
71A
72
TscH
TscL
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
40
1.25TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
74
75
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
TdoR
SDO data output rise time PIC16CXX
PIC16LCXX
—
10
20
10
—
25
45
25
50
ns
ns
ns
ns
76
77
TdoF
SDO data output fall time
—
TssH2doZ
10
SS↑ to SDO output hi-impedance
78
TscR
SCK output rise time
(Master mode)
PIC16CXX
—
10
20
10
—
—
—
25
45
ns
ns
ns
ns
ns
ns
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
—
—
25
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXX
50
PIC16LCXX
100
—
83
TscH2ssH,
TscL2ssH
1.5TCY + 40
SS ↑ after SCK edge
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605C-page 132
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
