PIC16C63A/65B/73B/74B
FIGURE 16-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
Symbol
TscH
TscL
Characteristic
Min
Typ† Max Units Conditions
No.
71
71A
72
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
(Slave mode)
40
1.25TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise
time
PIC16CXX
—
10
20
10
10
20
10
—
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXX
76
78
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(Master mode)
PIC16CXX
PIC16LCXX
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXX
PIC16LCXX
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 131
MICROCHIP [ MICROCHIP ]
