PIC16C63A/65B/73B/74B
FIGURE 16-11:
PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Param No.
Sym
Characteristic
Min Typ† Max Units
Conditions
62*
63*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
—
—
—
—
—
—
—
—
80
30
ns
ns
ns
ns
ns
TwrH2dtI
20
35
—
10
WR↑ or CS↑ to data in
PIC16CXX
invalid (hold time)
PIC16LCXX
64
TrdL2dtV
TrdH2dtI
RD↓ and CS↓ to data out valid
RD↑ or CS↑ to data out invalid
65*
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
2000 Microchip Technology Inc.
DS30605C-page 129
MICROCHIP [ MICROCHIP ]
