PIC16C63A/65B/73B/74B
FIGURE 16-18:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 16-4 for load conditions.
122
TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Sym
Characteristic
Min Typ† Max
Units Conditions
No.
120* TckH2dtV SYNC XMIT (MASTER &
SLAVE)
PIC16CXX
—
—
—
—
80
ns
ns
PIC16LCXX
100
Clock high to data out valid
121* Tckrf
122* Tdtrf
Clock out rise time and fall
time (Master mode)
PIC16CXX
—
—
—
—
—
—
—
—
45
50
45
50
ns
ns
ns
ns
PIC16LCXX
Data out rise time and fall time PIC16CXX
PIC16LCXX
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
FIGURE 16-19:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
125*
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup
time)
15
15
—
—
—
—
ns
ns
126*
TckL2dtl
Data hold after CK ↓ (DT hold time)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 136
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
