PIC16C63A/65B/73B/74B
FIGURE 16-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH,
TssL2scL
TCY
—
—
ns
SS↓ to SCK↓ or SCK↑ input
Continuous
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
71
71A
72
SCK input high time
(Slave mode)
TscH
TscL
TB2B
Single Byte
Continuous
Single Byte
40
1.25TCY + 30
40
ns (Note 1)
ns
SCK input low time
(Slave mode)
ns (Note 1)
72A
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns (Note 1)
73A
74
TscH2diL,
TscL2diL
100
ns
Hold time of SDI data input to SCK edge
PIC16CXX
—
10
20
10
25
45
25
ns
ns
ns
SDO data output rise
time
TdoR
75
PIC16LCXX
TdoF
—
76
77
SDO data output fall time
TssH2doZ
10
—
—
—
—
—
—
—
—
10
20
10
—
—
—
—
50
25
ns
ns
ns
ns
ns
ns
ns
ns
SS↑ to SDO output hi-impedance
PIC16CXX
SCK output rise time
(Master mode)
TscR
78
79
80
PIC16LCXX
45
TscF
25
SCK output fall time (Master mode)
PIC16CXX
50
TscH2doV,
TscL2doV
SDO data output valid
after SCK edge
PIC16LCXX
PIC16CXX
PIC16LCXX
100
50
SDO data output valid
after SS↓ edge
TssL2doV
82
83
100
TscH2ssH,
TscL2ssH
1.5TCY + 40
—
—
ns
SS ↑ after SCK edge
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2000 Microchip Technology Inc.
DS30605C-page 133
MICROCHIP [ MICROCHIP ]
