PIC12F635/PIC16F636/639
REGISTER 11-8: AFE STATUS REGISTER 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PEI
CHZACT
CHYACT
CHXACT
AGCACT
WAKEZ
WAKEY
WAKEX
ALARM
bit 8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(1)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
CHZACT: Channel Z Active bit (cleared via Soft Reset)
1= Channel Z is passing data after TAGC
0= Channel Z is not passing data after TAGC
(1)
CHYACT: Channel Y Active bit (cleared via Soft Reset)
1= Channel Y is passing data after TAGC
0= Channel Y is not passing data after TAGC
(1)
CHXACT: Channel X Active bit (cleared via Soft Reset)
1= Channel X is passing data after TAGC
0= Channel X is not passing data after TAGC
AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)
1= AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range.
0= AGC is inactive (Input signal is weak)
WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset)
1= Channel Z caused a AFE wake-up (passed ÷64 clock counter)
0= Channel Z did not cause a AFE wake-up
WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset)
1= Channel Y caused a AFE wake-up (passed ÷64 clock counter)
0= Channel Y did not cause a AFE wake-up
WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)
1= Channel X caused a AFE wake-up (passed ÷64 clock counter)
0= Channel X did not cause a AFE wake-up
ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read “Status Register command”)
1= The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the
Configuration register 0
0= The Alarm timer is not timed out
bit 0
PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred (real time)
1= A parity error has occurred and caused the ALERT output to go low
0= A parity error has not occurred
Note 1:
Bit is high whenever channel is passing data. Bit is low in Standby mode.
See Table 11-7 for the bit conditions of the AFE Status
Register after various SPI commands and the AFE
Power-on Reset.
TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND
VARIOUS SPI COMMANDS)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEI
Condition
CHZACT CHYACT CHXACT AGCACT WAKEZ
WAKEY
WAKEX
ALARM
POR
0
u
0
u
0
u
0
u
0
u
0
u
0
u
0
0
1
u
Read Command
(STATUS Register only)
Sleep Command
u
0
u
0
u
0
u
0
u
0
u
0
u
0
u
u
u
u
(1)
Soft Reset Executed
Legend:
u= unchanged
Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset
execution.
© 2007 Microchip Technology Inc.
DS41232D-page 127
MICROCHIP [ MICROCHIP ]
