PIC12F635/PIC16F636/639
REGISTER 11-6: CONFIGURATION REGISTER 5
R/W-0
AUTOCHSEL
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGCSIG
MODMIN1
MODMIN0
LCZSEN3
LCZSEN2
LCZSEN1
LCZSEN0
R5PAR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 8
AUTOCHSEL: Auto Channel Select bit
1= Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TSTAB; or otherwise, blocks the
channel(s).
0= Disabled – AFE follows channel enable/disable bits defined in Register 0
bit 7
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1= Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set
when the AGC begins regulating.
0= Disabled – the AFE passes signal of any level it is capable of detecting
bit 6-5
MODMIN<1:0>: Minimum Modulation Depth bit
00= 50%
01= 75%
10= 25%
11= 12%
bit 4-1
bit 0
LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit
0000= -0dB (Default)
:
1111= -30dB
R5PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Note 1: Assured monotonic increment (or decrement) by design.
REGISTER 11-7: COLUMN PARITY REGISTER 6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COLPAR7
COLPAR6
COLPAR5
COLPAR4
COLPAR3
COLPAR2
COLPAR1
COLPAR0
R6PAR
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd
number of set bits.
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain
an odd number of set bits.
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an
odd number of set bits.
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
DS41232D-page 126
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
