PIC12F635/PIC16F636/639
TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY
Register Name
Address
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5
Column Parity Register 6
AFE Status Register 7
0000
0001
0010
0011
0100
0101
0110
0111
OEH
DATOUT
RSSIFET CLKDIV
Unimplemented
Channel X Sensitivity Control
AUTOCHSEL AGCSIG MODMIN MODMIN
Column Parity Bits
AGCACT Wake-up Channel Indicators
OEL
ALRTIND
LCZEN
LCYEN
LCXEN
R0PAR
R1PAR
R2PAR
R3PAR
R4PAR
R5PAR
R6PAR
PEI
Channel X Tuning Capacitor
Channel Y Tuning Capacitor
Channel Z Tuning Capacitor
Channel Y Sensitivity Control
Channel Z Sensitivity Control
Active Channel Indicators
ALARM
REGISTER 11-1: CONFIGURATION REGISTER 0
R/W-0
OEH1
R/W-0
OEH0
R/W-0
OEL1
R/W-0
OEL0
R/W-0
R/W-0
LCZEN
R/W-0
R/W-0
LCXEN
R/W-0
ALRTIND
LCYEN
R0PAR
bit 8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 8-7
bit 6-5
OEH<1:0>: Output Enable Filter High Time (TOEH) bit
00= Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)
01= 1 ms
10= 2 ms
11= 4 ms
OEL<1:0>: Output Enable Filter Low Time (TOEL) bit
00= 1 ms
01= 1 ms
10= 2 ms
11= 4 ms
bit 4
bit 3
bit 2
bit 1
bit 0
ALRTIND: ALERT bit, output triggered by:
1= Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 “Alarm Timer”)
0= Parity error
LCZEN: LCZ Enable bit
1= Disabled
0= Enabled
LCYEN: LCY Enable bit
1= Disabled
0= Enabled
LCXEN: LCX Enable bit
1= Disabled
0= Enabled
R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
© 2007 Microchip Technology Inc.
DS41232D-page 123
MICROCHIP [ MICROCHIP ]
