PIC12F635/PIC16F636/639
REGISTER 11-4: CONFIGURATION REGISTER 3
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCZTUN5 LCZTUN4 LCZTUN3 LCZTUN2 LCZTUN1 LCZTUN0
R3PAR
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 8-7
bit 6-1
Unimplemented: Read as ‘0’
LCZTUN<5:0>: LCZ Tuning Capacitance bit
000000= +0 pF (Default)
:
111111= +63 pF
bit 0
R3PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set
bits
REGISTER 11-5: CONFIGURATION REGISTER 4
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCXSEN3 LCXSEN2 LCXSEN1 LCXSEN0 LCYSEN3 LCYSEN2 LCYSEN1 LCYSEN0
bit 8
R4PAR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 8-5
LCXSEN<3:0>(1): Typical LCX Sensitivity Reduction bit
0000= -0 dB (Default)
0001= -2 dB
0010= -4 dB
0011= -6 dB
0100= -8 dB
0101= -10 dB
0110= -12 dB
0111= -14 dB
1000= -16 dB
1001= -18 dB
1010= -20 dB
1011= -22 dB
1100= -24 dB
1101= -26 dB
1110= -28 dB
1111= -30 dB
bit 4-1
bit 0
LCYSEN<3:0>(1): Typical LCY Sensitivity Reduction bit
0000= -0 dB (Default)
:
1111= -30 dB
R4PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set
bits
Note 1: Assured monotonic increment (or decrement) by design.
© 2007 Microchip Technology Inc.
DS41232D-page 125
MICROCHIP [ MICROCHIP ]
