PIC12F635/PIC16F636/639
FIGURE 11-18:
SPI READ SEQUENCE
TCSH
TCSH
9
6
7
2
CS
10
4
8
16 Clocks for Read Result
16 Clocks for Read Command,
Address and Dummy Data
TCS
0
TCSSC
TSCCS
CSSC TCS1
TCSSC
TCS1
T
TCS0
T
HI
TLO
SCLK/ALERT
MSb
LSb
SCLK
(input)
SCLK
(input)
ALERT
(output)
ALERT
(output)
ALERT
(output)
1/FSCLK
1
TSU THD
T
DO
LFDATA/RSSI/
CCLK/SDIO
3
LFDATA
(output)
SDO
(output)
LFDATA
(output)
SDI
(input)
LFDATA
(output)
5
MCU SPI Read Details:
7.
8.
Drop CS.
1.
2.
Drive the AFE’s open collector ALERT output low.
To ensure no false clocks occur when CS drops.
Drop CS
•
•
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDO output.
•
Clock out 16-bit SPI Read result.
•
•
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDI input.
•
•
•
First seven bits clocked-out are dummy bits.
Next eight bits are the Configuration register data.
The last bit is the Configuration register row parity bit.
3.
4.
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
Driving SPI data.
Clock in 16-bit SPI Read sequence.
Command, address and dummy data.
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
•
9.
Raise CS to complete the SPI Read.
10. Change SCLK/ALERT back to input.
•
5.
6.
Note:
The TCSH is considered as one clock. Therefore, the
Configuration register data appears at 6th clock after TCSH.
DS41232D-page 120
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
