PIC12F609/615/12HV609/615
4.2.4.3
GP2/AN2(1)/T0CKI/INT/COUT/CCP1(1)/
P1A(1)
Note 1: PIC12F615/HV615 only.
Figure 4-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
(1)
• an analog input for the ADC
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from Comparator
(1)
• a Capture input/Compare input/PWM output
(1)
• a PWM output
FIGURE 4-2:
BLOCK DIAGRAM OF GP2
Analog(1)
Input Mode
VDD
Data Bus
D
Q
Q
Weak
CK
WR
WPU
C1OE
Enable
GPPU
VDD
RD
WPU
C1OE
1
0
D
Q
Q
I/O Pin
WR
CK
VSS
GPIO
D
Q
Q
WR
TRISIO
CK
RD
TRISIO
Analog(1)
Input Mode
RD
GPIO
D
Q
Q
Q
Q
D
CK
WR
IOC
Q1
EN
RD
IOC
D
S(2)
R
EN
Q
Interrupt-on-
Change
From other
GP<5:3, 1:0> pins
RD GPIO
To Timer0
To INT
Write ‘0’ to GBIF
To A/D Converter(3)
Note 1: Comparator mode and ANSEL determines Analog Input mode.
2: Set has priority over Reset.
3: PIC12F615/HV615 only.
DS41302A-page 36
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
