PIC12F609/615/12HV609/615
2.2.2.5
PIR1 Register
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
—
R/W-0
ADIF(1)
R/W-0
CCP1IF(1)
U-0
—
R/W-0
CMIF
U-0
—
R/W-0
TMR2IF(1)
R/W-0
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Interrupt Flag bit(1)
1= A/D conversion complete
0= A/D conversion has not completed or has not been started
CCP1IF: CCP1 Interrupt Flag bit(1)
bit 5
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1= Comparator output has changed (must be cleared in software)
0= Comparator output has not changed
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1)
1= Timer2 to PR2 match occurred (must be cleared in software)
0= Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Timer1 register overflowed (must be cleared in software)
0= Timer1 has not overflowed
Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
© 2006 Microchip Technology Inc.
Preliminary
DS41302A-page 19
MICROCHIP [ MICROCHIP ]
