PIC12F609/615/12HV609/615
TABLE 2-4:
PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 22, 101
1111 1111 16, 101
0000 0000 22, 101
0001 1xxx 15, 101
xxxx xxxx 22, 101
OPTION_REG
GPPU
Program Counter’s (PC) Least Significant Byte
IRP(1) RP1(1)
RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PCL
STATUS
FSR
TRISIO
—
PD
Z
DC
C
—
—
TRISIO5
TRISIO4 TRISIO3(4) TRISIO2
TRISIO1
TRISIO0 --11 1111 31, 101
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 22, 101
0000 0000 17, 101
GIE
—
PEIE
ADIE
T0IE
INTE
—
GPIE
CMIE
T0IF
—
INTF
GPIF(3)
CCP1IE
TMR2IE
TMR1IE -00- 0-00 18, 101
Unimplemented
—
—
—
PCON
—
—
—
—
—
—
—
—
POR
BOR
---- --qq 20, 101
Unimplemented
—
—
—
OSCTUNE
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000 29, 101
Unimplemented
—
—
PR2
APFCON
—
Timer2 Module Period Register
1111 1111 51, 101
P1ASEL ---0 --00 18, 101
—
—
—
T1GSEL
—
—
P1BSEL
Unimplemented
—
—
—
WPU(2)
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111 34, 101
--00 0000 34, 101
IOC
—
IOC3
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESL
ANSEL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1
xxxx xxxx 71, 101
-000 1111 33, 101
—
ANS0
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3:
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4:
TRISIO3 always reads as ‘1’ since it is an input only pin.
DS41302A-page 14
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
