PIC12F609/615/12HV609/615
FIGURE 2-2:
DATA MEMORY MAP OF
THE PIC12F609/HV609
FIGURE 2-3:
DATA MEMORY MAP OF
THE PIC12F615/HV615
File
File
File
File
Address
Address
Address
Address
Indirect Addr.(1)
Indirect Addr.(1)
Indirect Addr.(1)
OPTION_REG
PCL
Indirect Addr.(1)
OPTION_REG
PCL
00h
01h
02h
80h
81h
82h
00h
01h
02h
80h
81h
82h
TMR0
PCL
TMR0
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
GPIO
TRISIO
GPIO
TRISIO
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
TMR1L
TMR1H
PCON
OSCTUNE
T1CON
OSCTUNE
TMR2
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
APFCON
WPU
IOC
WPU
IOC
VRCON
VRCON
CMCON0
CMCON0
CMCON1
CMCON1
ADRESH
ADCON0
ADRESL
ANSEL
ANSEL
9Fh
A0h
9Fh
A0h
3Fh
40h
3Fh
40h
General
Purpose
Registers
General
Purpose
Registers
EFh
F0h
EFh
F0h
64 Bytes
Bank 0
Accesses 70h-7Fh
Bank 1
64 Bytes
Bank 0
Accesses 70h-7Fh
Bank 1
7Fh
FFh
7Fh
FFh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
DS41302A-page 10
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
