PIC12F609/615/12HV609/615
TABLE 2-1:
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx 22, 100
xxxx xxxx 41, 100
0000 0000 22, 100
0001 1xxx 15, 100
xxxx xxxx 22, 100
--x0 x000 31, 100
TMR0
PCL
STATUS
FSR
GPIO
—
Program Counter’s (PC) Least Significant Byte
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
GP5
GP4
GP3
GP2
GP1
GP0
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIR1
—
—
PEIE
—
—
T0IE
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 22, 100
0000 0000 17, 100
GIE
INTE
—
GPIE
CMIF
T0IF
—
INTF
—
GPIF
—
TMR1IF ---- 0--0 19, 100
Unimplemented
—
—
TMR1L
TMR1H
T1CON
—
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 45, 100
xxxx xxxx 45, 100
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON 0000 0000 49, 100
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CMVREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
—
—
—
—
—
—
—
VRCON
CMCON0
—
—
VRR
FVREN
CMPOL
VR3
—
VR2
VR1
—
VR0
0-00 0000 62, 101
0000 -0-0 58, 101
CMON
COUT
CMOE
CMR
CMCH
—
—
—
—
CMCON1
—
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC ---0 0-10 59, 101
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
IRP and RP1 bits are reserved, always maintain these bits clear.
© 2006 Microchip Technology Inc.
Preliminary
DS41302A-page 11
MICROCHIP [ MICROCHIP ]
