MCP23018/MCP23S18
1.6.6
CONFIGURATION REGISTER
Note:
The INTB pin is not bonded out on the
MCP23S18 (SPI) device in the 24-lead
QFN package. The MIRROR bit must be
configured to a “1” in order for interrupts to
be detected on PORTB.
The IOCON register contains several bits for
configuring the device:
The BANK bit changes how the registers are mapped
(see Table 1-4 and Table 1-5 for more details).
The MIRROR bit controls how the INTA and INTB pins
function with respect to each other.
• If BANK = 1, the registers associated with each
port are segregated. Registers associated with
PORTA are are mapped from address 00h - 0Ah
and registers associated with PORTB are
mapped from Address 10h - 1Ah
• When MIRROR = 1, the INTn pins are functionally
OR’ed so that an interrupt on either port will cause
both pins to activate
• If BANK = 0, the A/B registers are paired. For
example, IODIRA is mapped to address 00h and
IODIRB is mapped to the next address (address
01h). The mapping for all registers is from 00h -
15h
• When MIRROR = 0, the INT pins are separated.
Interrupt conditions on a port will cause its respec-
tive INT pin to activate
The Sequential Operation (SEQOP) controls the
incrementing function of the address pointer. If the
address pointer is disabled, the address pointer does
not automatically increment after each byte is clocked
during a serial transfer. This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
It is important to take care when changing the BANK bit
as the address mapping changes after the byte is
clocked into the device. The address pointer may point
to an invalid location after the bit is modified.
For example, if the device is configured to automati-
cally increment its internal address pointer the following
scenario would occur:
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuration.
• BANK = 0
The Interrupt Polarity (INTPOL) sets the polarity of the
INT pin. This bit is functional only when the ODR bit is
cleared, configuring the INT pin as active push-pull.
• Write 80h to 0Ah (IOCON) to set the BANK bit
• After the write completes the internal address now
points to 0Bh which is an invalid address when
the BANK bit is set
The Interrupt Clearing Control (INTCC) configures how
interrupts are cleared. When set (INTCC = 1), the
interrupt is cleared when the INTCAP register is read.
When cleared (INTCC = 0), the interrupt is cleared
when the GPIO register is read.
For this reason, it is advised to only perform byte writes
to this register when changing the BANK bit.
The interrupt can only be cleared when the interrupt
condition is inactive. Refer to Section 1.7.5 “Clearing
Interrupts” for details.
© 2008 Microchip Technology Inc.
DS22103A-page 23
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