MCP23018/MCP23S18
1.6.8
INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt.
This register is ‘read only’. Writes to this register will be
ignored.
REGISTER 1-10: INTF – INTERRUPT FLAG REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
INT7:INT0: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are
enabled (GPINTEN) <7:0>.
1= Pin caused interrupt.
0= Interrupt not pending.
DS22103A-page 26
© 2008 Microchip Technology Inc.
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