KSZ8041NL/RNL
TABLE 2-1:
Pin Number
KSZ8041NL PIN DESCRIPTION (CONTINUED)
Buffer Type
(Note 2-1)
Symbol
Description
LED Output: Programmable LED1 Output
Config mode: Latched as SPEED (register 0h, bit 13) during power-
up or reset. See Strap-In option – KSZ8041NL for details.
The LED1 pin is programmable via register 1Eh bits [15:14] and is
defined as follows:
LED Mode = [00]
Speed
10BT
Pin State
LED Definition
H
L
OFF
ON
100BT
31
LED1 / SPEED
Ipu/O
LED Mode = [01]
Activity
No Activity
Activity
Pin State
H
LED Definition
OFF
Toggle
Blinking
LED Mode = [10]
Reserved
LED Mode = [11]
Reserved
32
RST#
GND
I
Chip Reset (active low)
Ground
PADDLE
Gnd
Note 2-1
P = Power supply
Gnd = Ground
I = Input
O = Output
I/O = Bi-directional
Ipd = Input with internal pull-down (40K ±30%)
Ipu = Input with internal pull-up (40K ±30%)
Opu = Output with internal pull-up (40K ±30%)
Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.
Note 2-2
Note 2-3
Note 2-4
MII Rx mode: The RXD[3:0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3:0]
presents a valid data to the MAC through the MII. RXD[3:0] is invalid when RXDV is deasserted.
RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which
CRS_DV is asserted, two bits of recovered data are sent from the PHY.
MII Tx mode: The TXD[3:0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3:0]
presents a valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is
deasserted.
Note 2-5
RMII Tx mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which
TX_EN is asserted, two bits of data are received by the PHY from the MAC.
DS00002245B-page 10
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
