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KSZ8041NL-AM 参数 Datasheet PDF下载

KSZ8041NL-AM图片预览
型号: KSZ8041NL-AM
PDF下载: 下载PDF文件 查看货源
内容描述: [IC TXRX PHY 10/100 AUTO 32-MLF]
分类和应用: 局域网(LAN)标准以太网:16GBASE-T电信电信集成电路
文件页数/大小: 58 页 / 1576 K
品牌: MICROCHIP [ MICROCHIP ]
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KSZ8041NL/RNL  
TABLE 2-1:  
Pin Number  
KSZ8041NL PIN DESCRIPTION (CONTINUED)  
Buffer Type  
Symbol  
Description  
(Note 2-1)  
7
8
TX+  
XO  
I/O  
Physical transmit or receive signal (+ differential)  
Crystal Feedback.  
This pin is used only in MII mode when a 25-MHz crystal is used.  
This pin is a no connect if an oscillator or an external clock source is  
used, or if RMII mode is selected.  
O
Crystal/Oscillator/External Clock Input:  
MII mode: 25 MHz ±50 ppm (crystal, oscillator, or external clock)  
RMII mode: 50 MHz ±50 ppm (oscillator or external clock only)  
XI /  
REFCLK  
9
I
Set physical transmit output current.  
Connect a 6.49-Kresistor in parallel with a 100-pF capacitor to  
ground on this pin.  
10  
REXT  
I/O  
Management Interface (MII) Data I/O  
This pin requires an external 4.7-Kpull-up resistor.  
11  
12  
MDIO  
MDC  
I/O  
I
Management Interface (MII) Clock Input  
This pin is synchronous to the MDIO data interface.  
MII mode: Receive Data Output[3] (Note 2-2)  
Config mode: The pull-up/pull-down value is latched as PHY-  
ADDR[0] during power-up or reset. See “Strap-In option –  
KSZ8041NL” for details.  
RXD3 /  
PHYAD0  
13  
14  
Ipu/O  
Ipd/O  
MII mode: Receive Data Output[2] (Note 2-2)  
Config mode: The pull-up/pull-down value is latched as PHY-  
ADDR[1] during power-up or reset. See “Strap-In option –  
KSZ8041NL” for details.  
RXD2 /  
PHYAD1  
MII mode: Receive Data Output[1] (Note 2-2)  
RMII mode: Receive Data Output[1] (Note 2-3)  
Config mode: The pull-up/pull-down value is latched as PHY-  
ADDR[2] during power-up or reset. See “Strap-In option –  
KSZ8041NL” for details.  
RXD1 /  
RXD[1] /  
PHYAD2  
15  
Ipd/O  
MII mode: Receive Data Output[0] (Note 2-2).  
RMII mode: Receive Data Output[0] (Note 2-3).  
Config mode: Latched as DUPLEX (register 0h, bit 8) during power-  
up or reset. See “Strap-In option – KSZ8041NL” for details.  
RXD0 /  
RXD[0] /  
DUPLEX  
16  
17  
Ipu/O  
P
3.3V Digital VDD  
VDDIO_3.3  
MII mode: Receive Data Valid Output  
RXDV /  
CRSDV /  
CONFIG2  
RMII mode: Carrier Sense/Receive Data Valid Output  
Config mode: The pull-up/pull-down value is latched as CONFIG2  
during power-up or reset. See “Strap-In option – KSZ8041NL”  
18  
19  
20  
Ipd/O  
O
for details.  
MII mode: Receive Clock Output  
RXC  
MII mode: Receive Error Output  
RMII mode: Receive Error Output  
Config mode: The pull-up/pull-down value is latched as ISOLATE  
during power-up or reset. See “Strap-In option – KSZ8041NL” for  
details.  
RXER /  
RX_ER /  
ISO  
Ipd/O  
2017 Microchip Technology Inc.  
DS00002245B-page 7  
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