KSZ8041NL/RNL
2.0
2.1
PIN DESCRIPTION AND CONFIGURATION
KSZ8041NL Pin Description and Configuration
FIGURE 2-1:
KSZ8041NL 32-QFN PIN ASSIGNMENT (TOP VIEW)
32 31 30 29 28 27 26 25
1
2
24
23
GND
VDDPLL_1.8
VDDA_3.3
RX-
TXD0/TXD[0]
TXEN/TX_EN
3
4
5
22 TXC
21
INTRP
RXER/RX_ER/ISO
RXC
RXDV/CRSDV/CONFIG2
VDDIO_3.3
Paddle Ground
on bottom of chip
20
RX+
TX-
TX+
XO
6
7
8
19
18
17
9
10 11 12 13 14 15 16
TABLE 2-1:
Pin Number
KSZ8041NL PIN DESCRIPTION
Buffer Type
Symbol
Description
(Note 2-1)
1
2
GND
Gnd
P
Ground
1.8V Analog VDD
Decouple with 1.0-µF and 0.1-µF capacitors to ground.
VDDPLL_1.8
3
4
5
6
VDDA_3.3
RX-
P
3.3V Analog VDD
I/O
I/O
I/O
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
RX+
TX-
DS00002245B-page 6
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
