KSZ8041NL/RNL
2.0
2.1
PIN DESCRIPTION AND CONFIGURATION
KSZ8041NL Pin Description and Configuration
KSZ8041NL 32-QFN PIN ASSIGNMENT (TOP VIEW)
FIGURE 2-1:
RST#
LED1/SPEED
LED0/NWAYEN
CRS/CONFIG1
COL/CONFIG0
TXD3
TXD2
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
TX+
XO
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Paddle Ground
on bottom of chip
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
15 16
TXD1/TXD[1]
TXD0/TXD[0]
TXEN/TX_EN
TXC
INTRP
RXER/RX_ER/ISO
RXC
RXDV/CRSDV/CONFIG2
VDDIO_3.3
RXD0/RXD[0]/DUPLEX
TABLE 2-1:
Pin Number
1
2
3
4
5
6
KSZ8041NL PIN DESCRIPTION
Symbol
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
Buffer Type
Gnd
P
P
I/O
I/O
I/O
Ground
1.8V Analog V
DD
Decouple with 1.0-µF and 0.1-µF capacitors to ground.
3.3V Analog V
DD
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Description
XI/REFCLK
REXT
MDIO
MDC
RXD3/PHYAD0
RXD2/PHYAD1
RXD1/RXD[1]/PHYAD2
DS00002245B-page 6
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
