KSZ8041NL/RNL
2.2
STRAP-IN OPTION – KSZ8041NL
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISO-
LATE mode, or is not configured with an incorrect PHY Address.
TABLE 2-2:
STRAP-IN OPTION – KSZ8041NL
Type
Pin
Number
Pin Name
Pin Function
(Note 2-1)
15
14
PHYAD2
PHYAD1
Ipd/O
Ipd/O
The PHY Address is latched at power-up or reset and is configurable to any
value from 1 to 7.
The default PHY Address is 00001.
13
PHYAD0
Ipu/O
PHY Address bits [4:3] are always set to ‘00’.
18
29
CONFIG2
CONFIG1
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up or reset and are
defined as follows:
CONFIG[2:0]
000
Mode
MII (default)
001
RMII
010
Reserved - not used
Reserved - not used
MII 100 Mbps Preamble Restore
Reserved - not used
Reserved - not used
Reserved - not used
011
28
CONFIG0
Ipd/O
100
101
110
111
ISOLATE mode:
Pull-up = Enable
Pull-down (default) = Disable
During power-up or reset, this pin value is latched into register 0h bit 10.
20
31
ISO
Ipd/O
Ipu/O
SPEED mode:
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
During power-up or reset, this pin value is latched into register 0h bit 13 as
the Speed Select, and also is latched into register 4h (Auto-Negotiation
Advertisement) as the Speed capability support.
SPEED
DUPLEX mode:
Pull-up (default) = Half Duplex
16
DUPLEX
NWAYEN
Ipu/O
Ipu/O
Pull-down = Full Duplex
During power-up or reset, this pin value is latched into register 0h bit 8 as
the Duplex mode.
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
30
During power-up or reset, this pin value is latched into register 0h bit 12.
Note 2-1
Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise.
2017 Microchip Technology Inc.
DS00002245B-page 11
MICROCHIP [ MICROCHIP ]
