KSZ8041NL/RNL
TABLE 2-3:
Pin Number
KSZ8041RNL PIN DESCRIPTION (CONTINUED)
Pin Name
Type (Note 2-1)
Pin Function
Management Interface (MII) Data I/O
This pin requires an external 4.7-k pull-up resistor.
11
12
MDIO
I/O
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MDC
I
The pull-up/pull-down value is latched as PHYADDR[0]
during power-up or reset. See Strap-In option –
KSZ8041RNL for details.
13
14
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[1]
during power-up or reset. See Strap-In option –
KSZ8041RNL for details.
PHYAD1
Ipd/O
Ipd/O
RMII mode: RMII Receive Data Output[1] (Note 2-2)
Config mode: The pull-up/pull-down value is latched as
PHYADDR[2] during power-up or reset. See Strap-In option
– KSZ8041RNL for details.
RXD1 /
PHYAD2
15
RMII mode: RMII Receive Data Output[0]] (Note 2-2)
Config mode: Latched as DUPLEX (register 0h, bit 8) during
power-up or reset. See Strap-In option – KSZ8041RNL for
details.
RXD0 /
DUPLEX
16
17
18
Ipu/O
P
VDDIO_3.3
3.3V Digital VDD
RMII mode: Carrier Sense/Receive Data Valid Output
Config mode: The pull-up/pull-down value is latched as
CONFIG2 during power-up or reset. See Strap-In option –
KSZ8041RNL for details.
CRSDV /
CONFIG2
Ipd/O
50 MHz Clock Output
19
20
REF_CLK
O
This pin provides the 50-MHz RMII reference clock output to
the MAC.
RMII mode: Receive Error Output.
RXER /
RX_ER /
ISO
Config mode: The pull-up/pull-down value is latched as ISO-
LATE during power-up or reset. See Strap-In option –
KSZ8041RNL for details.
Ipd/O
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for pro-
gramming the interrupt conditions and reading the interrupt
status. Register 1Fh bit 9 sets the interrupt output to active
low (default) or active high.
21
INTRP
Opu
No Connect
22
23
24
25
26
27
NC
TX_EN
TXD0
TXD1
NC
O
I
RMII Transmit Enable Input
RMII Transmit Data Input[0] (Note 2-3)
RMII Transmit Data Input[1] (Note 2-3)
No Connect
I
I
I
No Connect
NC
I
The pull-up/pull-down value is latched as CONFIG0 during
power-up or reset. See Strap-In option – KSZ8041RNL for
details.
28
29
CONFIG0
CONFIG1
Ipd/O
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 during
power-up or reset. See Strap-In option – KSZ8041RNL for
details.
2017 Microchip Technology Inc.
DS00002245B-page 13
MICROCHIP [ MICROCHIP ]
