13.5 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp
indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or
alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and
other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram shown in Figure 13-3. The elements of the block diagram that are
not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indicates the
Timer/Counter number.
Figure 13-3. Input Capture Unit Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
ICRnH (8-bit)
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
WRITE
Analog Comparator 1 Interrupt
ICPSEL1
AC1ICE
ICNC
ICES
ICPnA
Noise
Canceler
Edge
Detector
ICFn (Int. Req.)
ICPnB
When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively on the analog comparator
output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is
triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag
(ICFn) is set at the same system clock as the TCNTn value is copied into ICRn register. If enabled (ICIEn = 1), the input
capture flag generates an input capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed.
Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high
byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the
CPU reads the ICRnH I/O location it will access the TEMP register.
The ICRn register can only be written when using a waveform generation mode that utilizes the ICRn register for defining the
counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can
be written to the ICRn register. When writing the ICRn register the high byte must be written to the ICRnH I/O location before
the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to Section 13.2 “Accessing 16-bit Registers” on page 94.
The ICF1 output can be used to retrigger the timer counter. It has the same effect than the TOP signal.
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ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
