The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the input
capture pin (ICPn). The input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing
noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCRnA register, the ICRn register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the
OCRnA register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered
allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn register can be used as an
alternative, freeing the OCRnA to be used as PWM output.
13.1.2 Definitions
The following definitions are used extensively throughout the section:
BOTTOM
MAX
The counter reaches the BOTTOM when it becomes 0x0000.
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the
OCRnA or ICRn register. The assignment is dependent of the mode of operation.
13.2 Accessing 16-bit Registers
The TCNTn, OCRnx, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit
register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary
storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each
16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is
written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit
register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register
is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnx 16-bit registers does not involve
using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the
temporary register. The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when
using “C”, the compiler handles the 16-bit access.
Assembly Code Examples(1)
...
; Set TCNTn to 0x01FF
ldi
ldi
out
out
r17,0x01
r16,0xFF
TCNTnH,r17
TCNTnL,r16
; Read TCNTn into r17:r16
in
in
r16,TCNTnL
r17,TCNTnH
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...
Note:
1. The example code assumes that the part specific header file is included.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
94
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
