13.4 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block
diagram of the counter and its surroundings.
Figure 13-2. Counter Unit Block Diagram
DATA BUS (8-bit)
TOVn
(Int. Req.)
TEMP (8-bit)
Clock Select
Count
Clear
Edge
Tn
TCNTnH (8-bit)
TCNTnL (8-bit)
clkTn
Detector
Control Logic
TOP
Direction
TCNTnH (16-bit Counter)
(From Prescaler)
RTG
BOTTOM
Signal description (internal signals):
Count
Direction
Clear
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
clkTn
TOP
Signalize that TCNTn has reached maximum value.
BOTTOM
RTG
Signalize that TCNTn has reached minimum value (zero).
An external event (ICP1A or ICP1B) asks for a TOP like action.
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of
the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly
accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte
temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the
entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases
of writing to the TCNTn register when the counter is counting that will give unpredictable results. The special cases are
described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn).
The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no
clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU,
independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the
Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details about
advanced counting sequences and waveform generation, see Section 13. “16-bit Timer/Counter1 with PWM” on page 92.
The Timer/Counter overflow flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can
be used for generating a CPU interrupt.
ATmega16/32/64/M1/C1 [DATASHEET]
97
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
