13.5.1 Input Capture Trigger Source
The trigger sources for the input capture unit are the Input Capture pin (ICP1A and ICP1B).
Be aware that changing trigger source can trigger a capture. The input capture flag must therefore be cleared after the
change.
The Input Capture pin (ICPn) IS sampled using the same technique as for the Tn pin (Figure 11-1 on page 75). The edge
detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector,
which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always
enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
13.5.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored
over four samples, and all four must be equal for changing the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B
(TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied
to the input, to the update of the ICRn register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
13.5.3 Using the Input Capture Unit
The main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming
events. The time between two events is critical. If the processor has not read the captured value in the ICRn register before
the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the input capture interrupt, the ICRn register should be read as early in the interrupt handler routine as possible.
Even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the input capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation,
is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the
edge sensing must be done as early as possible after the ICRn register has been read. After a change of the edge, the input
capture flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICFn flag is not required (if an interrupt handler is used).
13.5.4 Using the Input Capture Unit as TCNT1 Retrigger Input
TCNT1 counts from BOTTOM to TOP. The TOP value can be a fixed value, ICR1, or OCR1A. When enabled the retrigger
input forces to reach the TOP value. It means that ICF1 output is ored with the TOP signal.
13.6 Output Compare Units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx
the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled
(OCIEnx = 1), the output compare flag generates an output compare interrupt. The OCFnx flag is automatically cleared
when the interrupt is executed. Alternatively the OCFnx flag can be cleared by software by writing a logical one to its I/O bit
location. The waveform generator uses the match signal to generate an output according to operating mode set by the
Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see
Section 13. “16-bit Timer/Counter1 with PWM” on page 92)
A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In
addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform
generator.
Figure 13-4 shows a block diagram of the output compare unit. The small “n” in the register and bit names indicates the
device number (n = n for Timer/Counter n), and the “x” indicates output compare unit (x). The elements of the block diagram
that are not directly a part of the output compare unit are gray shaded.
ATmega16/32/64/M1/C1 [DATASHEET]
99
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
