13.7.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the
COMnx1:0 = 0 tells the waveform generator that no action on the OCnx register is to be performed on the next compare
match. For compare output actions in the non-PWM modes refer to Table 13-1 on page 110. For fast PWM mode refer to
Table 13-2 on page 110, and for phase correct and phase and frequency correct PWM refer to Table 13-3 on page 111.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the FOCnx strobe bits.
13.8 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of
the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits
do not affect the counting sequence, while the waveform generation mode bits do. The COMnx1:0 bits control whether the
PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits
control whether the output should be set, cleared or toggle at a compare match (see Section 13.7 “Compare Match Output
Unit” on page 101). For detailed timing information refer to Section 13.9 “Timer/Counter Timing Diagrams” on page 108.
13.8.1 Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value
(MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag
(TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves like a 17th
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the
TOVn flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a
new counter value can be written anytime.
The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external
events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt
or the prescaler must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output compare to generate
waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
13.8.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn register are used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA
(WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in Figure 13-6. The counter value (TCNTn) increases until a compare match
occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared.
Figure 13-6. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(COMnA1:0 = 1)
(Toggle)
1
2
3
4
Period
102
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
