Figure 13-1. 16-bit Timer/Counter Block Diagram(1)
TOVn (Int. Req.)
Clock Select
Count
Clear
Direction
Control Logic
Edge
Detector
Tn
clkTn
(from Prescaler)
RTG
TOP
BOTTOM
Timer/Counter
TCNTn
=
= 0
OCnA (Int. Req.)
Waveform
Generation
OCnA
OCnB
=
OCRnA
Fixed
TOP
Value
OCnB (Int. Req.)
Waveform
Generation
=
OCRnB
AC1ICE
ICPSEL1
ICFn (Int. Req.)
ICPnA
ICPnB
0
1
Edge
Detector
Noise
Canceler
ICRn
TCCRnA
TCCRnB
Analog Comparator 1
Interrupt
Note:
1. Refer to Table on page 5 for Timer/Counter 1 pin placement and description.
13.1.1 Registers
The Timer/Counter (TCNTn), output compare registers (OCRnx), and input capture register (ICRn) are all 16-bit registers.
Special procedures must be followed when accessing the 16-bit registers. These procedures are described in Section 13.2
“Accessing 16-bit Registers” on page 94. The Timer/Counter control registers (TCCRnx) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag
register (TIFRn). All interrupts are individually masked with the timer interrupt mask register (TIMSKn). TIFRn and TIMSKn
are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The clock select
logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clkTn).
The double buffered output compare registers (OCRnx) are compared with the Timer/Counter value at all time. The result of
the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output
compare pin (OCnx). See Section 13.6 “Output Compare Units” on page 99 The compare match event will also set the
compare match flag (OCFnx) which can be used to generate an output compare interrupt request.
ATmega16/32/64/M1/C1 [DATASHEET]
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