When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 5-6 on page 29.
Table 5-6. Start-up times for the internal calibrated RC Oscillator clock selection
Start-up Time from Power-down and
Power-save
Additional Delay from Reset
(VCC = 5.0V)
Power Conditions
BOD enabled
SUT1..0
00
6 CK
6 CK
14CK(1)
Fast rising power
Slowly rising power
14CK + 4.1ms
14CK + 65ms(2)
01
6 CK
10
Reserved
11
Notes: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.
5.5.1 Oscillator Calibration Register – OSCCAL
Bit
7
6
5
4
3
2
1
0
CAL7
R/W
CAL6
R/W
CAL5
R/W
CAL4
R/W
CAL3
R/W
CAL2
R/W
CAL1
R/W
CAL0
R/W
OSCCAL
Read/Write
Initial Value
Device Specific Calibration Value
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from the
oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator
frequency of 8.0MHz at 25°C. The application software can write this register to change the oscillator frequency. The
oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within ±1% accuracy. Calibration outside that range is
not guaranteed.
Note that this oscillator is used to time EEPROM and flash write accesses, and these write times will be affected accordingly.
If the EEPROM or flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range,
setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of
OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in
that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency
increment of less than 2% in the frequency range 7.3 - 8.1MHz.
5.6
PLL
5.6.1 Internal PLL
The internal PLL in the Atmel® ATmega16/32/64/M1/C1 generates a clock frequency that is 64x multiplied from its nominal
1MHz input. The source of the 1MHz PLL input clock can be:
●
●
●
the output of the internal RC oscillator divided by 8
the output of the crystal oscillator divided by 8
the external clock divided by 8
See Figure 5-3 on page 30.
When the PLL is locked on the RC Oscillator, adjusting the RC Oscillator via OSCCAL Register, will also modify the PLL
clock output. However, even if the possibly divided RC Oscillator is taken to a higher frequency than 8MHz, the PLL output
clock frequency saturates at 70MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that
the PLL in this case is not locked any more with its 1MHz source clock.
ATmega16/32/64/M1/C1 [DATASHEET]
29
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
