5.
5.1
System Clock
Clock Systems and their Distribution
Figure 5-1
presents the principal clock systems in the AVR
®
and their distribution. All of the clocks need not be active at a
given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep
Section 6. “Power Management and Sleep Modes” on page 34.
The clock systems are detailed
below.
Figure 5-1. Clock Distribution
Fast Peripherals
General I/O
Modules
ADC
CPU Core
RAM
Flash and
EEPROM
clk
PLL
PLL
clk
I/O
clk
ADC
clk
CPU
clk
FLASH
AVR Clock
Control Unit
Reset Logic
Watchdog Timer
Source Clock
Watchdog Clock
PLL Input
Multiplexer
Clock
Multiplexer
Watchdog
Oscillator
External Clock
Crystal
Oscillator
Calibrated RC
Oscillator
5.1.1
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are
the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU
clock inhibits the core from performing general operations and calculations.
5.1.2
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, UART. The I/O clock is also used by the
External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such
interrupts to be detected even if the I/O clock is halted.
5.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The flash clock is usually active simultaneously with the CPU clock.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
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