5.6.2 PLL control and status register – PLLCSR
Bit
7
–
6
–
5
–
4
–
3
–
2
PLLF
R/W
0
1
0
$29 ($29)
Read/Write
Initial Value
PLLE
R/W
0/1
PLOCK
PLLCSR
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC oscillator is started as PLL reference clock. If
PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLKPLL for Fast Peripherals.
After the PLL is enabled, it takes about 100µs for the PLL to lock.
5.7
5.8
128 kHz Internal Oscillator
The 128 kHz internal oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and
25°C. This clock is used by the Watchdog Oscillator.
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 5-4. To run the device on an
external clock, the CKSEL fuses must be programmed to “0000”.
Figure 5-4. External Clock Drive Configuration
NC
XTAL2
XTAL1
GND
EXTERNAL
CLOCK
SIGNAL
Table 5-8. External Clock Frequency
CKSEL3..0
Frequency Range
0 - 16MHz
0000
ATmega16/32/64/M1/C1 [DATASHEET]
31
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
