Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 8MHz in order to keep the PLL
in the correct operating range.
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR
is set when PLL is locked.
Both internal 8MHz RC Oscillator, Crystal Oscillator and PLL are switched off in Power-down and Standby sleep
modes.01/15
Table 5-7. Start-up Times when the PLL is selected as system clock
Start-up Time from Power-down and
Power-save
Additional Delay from Reset
(VCC = 5.0V)
CKSEL3..0
SUT1..0
00
1K CK
1K CK
1K CK
16K CK
1K CK
1K CK
16K CK
16K CK
6 CK(1)
6 CK(1)
6 CK(1)
14CK
0011
01
14CK + 4ms
14CK + 64ms
14CK
RC Osc
10
11
00
14CK
0101
01
14CK + 4ms
14CK + 4ms
14CK + 64ms
14CK
Ext Osc
10
11
00
0001
01
14CK + 4ms
14CK + 64ms
Ext Clk
10
11
Reserved
Note:
1. This value do not provide a proper restart; do not use PD in this clock scheme.
Figure 5-3. PLL Clocking System
OSCCAL
CKSEL3..0
PLLE
PLLF
Lock
Detector
PLOCK
CLKPLL
RC Oscillator
8MHz
Divide
by 8
PLL
64x
Divide
by 2
Divide
by 4
CKSOURCE
XTAL1
Oscillators
XTAL2
30
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
