When this clock source is selected, start-up times are determined by the SUT fzses as shown in Table 5-9.
Table 5-9. Start-up Times for the External Clock Selection
Start-up Time from Power-down and Additional Delay from Reset
SUT1..0
00
Power-save
(VCC = 5.0V)
Recommended Usage
BOD enabled
6 CK
14CK
01
6 CK
14CK + 4.1ms
14CK + 65ms
Reserved
Fast rising power
10
6 CK
Slowly rising power
11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable
operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable
behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency.
Note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation. Refer to Section 5.10 “System Clock Prescaler” on page 32 for details.
5.9
Clock Output Buffer
When the CKOUT fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when chip clock is
used to drive other circuits on the system. The clock will be output also during reset and the normal operation of I/O pin will
be overridden when the fuse is programmed. Any clock source, including internal RC oscillator, can be selected when CLKO
serves as clock output. If the system clock prescaler is used, it is the divided system clock that is output (CKOUT fuse
programmed).
5.10 System Clock Prescaler
The Atmel® ATmega16/32/64/M1/C1 system clock can be divided by setting the clock prescale register – CLKPR. This
feature can be used to decrease power consumption when the requirement for processing power is low. This can be used
with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC
clkCPU, and clkFLASH are divided by a factor as shown in Table 5-10.
,
When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system.
It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at
the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to
the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2
before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock
period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:
1. Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
32
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
