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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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5.10.1 Clock Prescaler Register – CLKPR  
Bit  
7
CLKPCE  
R/W  
6
5
4
3
2
1
0
CLKPS3 CLKPS2 CLKPS1 CLKPS0  
R/W R/W R/W R/W  
See Bit Description  
CLKPR  
Read/Write  
Initial Value  
R
0
R
0
R
0
0
• Bit 7 – CLKPCE: Clock Prescaler Change Enable  
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the  
other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when  
CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor  
clear the CLKPCE bit.  
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0  
These bits define the division factor between the selected clock source and the internal system clock. These bits can be  
written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input  
to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are  
given in Table 5-10.  
The CKDIV8 fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to  
“0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should  
be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present  
operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 fuse setting. The  
application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher  
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the  
CKDIV8 fuse programmed.  
Table 5-10. Clock Prescaler Select  
CLKPS3  
CLKPS2  
CLKPS1  
CLKPS0  
Clock Division Factor  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
4
8
16  
32  
64  
128  
256  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
ATmega16/32/64/M1/C1 [DATASHEET]  
33  
7647O–AVR–01/15  
 
 
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